DIS_TCP_EF=Val_0x0, RSF=Val_0x0, FUP=Val_0x0, FEP=Val_0x0, RTC=Val_0x0
Queue 0 Receive Operation Mode Register
| RTC | Receive Queue Threshold Control These bits control the threshold level of the MTL Rx Queue (in bytes):The received packet is transferred to the application or DMA when the packet size within the MTL Rx Queue is larger than the threshold. In addition, full packets with length less than the threshold are automatically transferred. This field is valid only when the RSF bit is zero. This field is ignored when the RSF bit is set to 1. 0 (Val_0x0): 64 1 (Val_0x1): 32 2 (Val_0x2): 96 3 (Val_0x3): 128 |
| FUP | Forward Undersized Good Packets When this bit is set, the Rx Queue forwards the undersized good packets (packets with no error and length less than 64 bytes), including pad-bytes and CRC. When this bit is reset, the Rx Queue drops all packets of less than 64 bytes, unless a packet is already transferred because of the lower value of Rx Threshold, for example, RTC = 01. 0 (Val_0x0): Forward undersized good packets is disabled 1 (Val_0x1): Forward undersized good packets is enabled |
| FEP | Forward Error Packets When this bit is reset, the Rx Queue drops packets with error status (CRC error, GMII_ER, watchdog timeout, or overflow). However, if the start byte (write) pointer of a packet is already transferred to the read controller side (in Threshold mode), the packet is not dropped. When this bit is set, all packets except the runt error packets are forwarded to the application or DMA. If the RSF bit is set and the Rx Queue overflows when a partial packet is written, the packet is dropped irrespective of the setting of this bit. However, if the RSF bit is reset and the Rx Queue overflows when a partial packet is written, a partial packet may be forwarded to the application or DMA. 0 (Val_0x0): Forward error packets is disabled 1 (Val_0x1): Forward error packets is enabled |
| RSF | Receive Queue Store and Forward When this bit is set, the ETH module reads a packet from the Rx Queue only after the complete packet has been written to it, ignoring the RTC field of this register. When this bit is reset, the Rx Queue operates in the Threshold (cut-through) mode, subject to the threshold specified by the RTC field of this register. 0 (Val_0x0): Receive queue store and forward is disabled 1 (Val_0x1): Receive queue store and forward is enabled |
| DIS_TCP_EF | Disable Dropping of TCP/IP Checksum Error Packets When this bit is set, the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine. Such packets have errors only in the encapsulated payload. There are no errors (including FCS error) in the Ethernet packet received by the MAC. When this bit is reset, all error packets are dropped if the FEP bit is reset. 0 (Val_0x0): Dropping of TCP/IP checksum error packets is enabled 1 (Val_0x1): Dropping of TCP/IP checksum error packets is disabled |